4 case studies · 5 smaller builds · 2025 – present

Work

Everything I have built so far, with the checks behind it.

4 projects · 1 in progress

Case studies

A DVI video pipeline in Verilog: timing, pattern, TMDS encoder; serializer in progress.

decode(encode(d)) == d on every symbol, against an independent decoder.

Run-on-boot C firmware for a PYNQ-Z2 rover that hunts colored cubes and coordinates with a partner over MQTT.

Cubes confirmed by a 6-read burst vote, ≥2 within 5 cm.

Schematic, 4-layer PCB, power path and ESP32-S3R8 firmware; Bluetooth or microSD into an I2S DAC.

A design study, stopped before any board was built or bench-tested.

A distributed baby-monitoring cradle: four PYNQ-Z2 subsystems over UART.

RMS with noise-floor subtraction on a pthread capture loop.

5 builds · 1 in progress

Verilog · 5EIC0
32-bit counter from gate logic
Half-adders from an XOR and an AND, full-adders from two half-adders, a 32-bit ripple adder from 32 of those, and a clocked counter with enable and reset on top, interfaced to an AXI4-Lite bus so a processor can configure it. Simulated, then run on the PYNQ board.
Verilog · C · 5EIC0
EduRV RISC-V labs
Labs on EduRV, an educational RISC-V core: simulating it in Verilator, working with it in Vivado, and writing C code that runs on the core itself.
Verilog · in progress
I²C master
A reusable configuration block for the HDMI transmitter — reading the sink’s EDID over DDC — and, later, an audio DAC. So far only the module interface exists: address, data and an enable strobe in; SCL and a bidirectional SDA out. Body and testbench still to be written.

C · libpynq
Function plotter
An oscilloscope-style plotter that draws equations, with axes, on the 240×240 TFT: sine and cosine, alone or together, from 360-entry lookup tables, scaled by an adjustable ratio.
C · libpynq
Snake
A tick-based game loop: the snake moves every 200 ms, but the loop polls the buttons every 10 ms, keeps the last valid direction and rejects a 180° reversal, so input feels instant.